Watchdog timer

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The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software deadlock and automatic recovery.
To protect the system against software deadlock, the user software must refresh the WDT within a user-defined time period. If the software fails to do this periodical refresh, an internal hardware reset will be initiated if enabled (WDRE = 1). The software can be designed such that the WDT times out if the program does not work properly.

• Power-on Reset
At initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algorithm has weakly pulled all pins HIGH. Powering up the device without a valid reset could cause the MCU to start executing instructions from an indeterminate location. Such undefined states may inadvertently corrupt the code in the flash.
When power is applied to the device, the RST pin must be held HIGH long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. An example of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 mF capacitor and to VSS through an 8.2 kW resistor. For a low frequency oscillator with slow start-up time the reset signal must be extended in order to account for the slow start-up time. This method maintains the necessary relationship between VDD and RST to avoid programming at an indeterminate location, which may cause corruption in the code of the flash. The power-on detection is designed to work as power-up initially, before the voltage reaches the brown-out detection level. The POF flag in the PCON register is set to indicate an initial power-up condition. The POF flag will remain active until cleared by software. Please refer to the PCON register definition for detail information. Following reset, the P89V51RD2 will either enter the Soft ICE mode (if previously enabled via ISP command) or attempt to auto baud to the ISP boot loader. If this auto baud is not successful within about 400 ms, the device will begin execution of the user code