SPI features

• LSB first or MSB first data transfer
• Four programmable bit rates
• End of transmission (SPIF)
• Write collision flag protection (WCOL)
• Wake-up from idle mode (slave mode only)
SPI description
The serial peripheral interface (SPI) allows high-speed
Synchronous data transfer between the P89V51RD2 and peripheral devices or between several P89V51RD2 devices. Figure 16 shows the correspondence between master and slave SPI devices. The SCK pin is the clock output and input for the master and slave modes, respectively. The SPI clock generator will start following a write to the master devices
SPI data register. The written data is then shifted out of the MOSI pin on the master device into the MOSI pin of the slave device. Following a complete transmission of one byte of data, the SPI clock generator is stopped and the SPIF flag is set. An SPI interrupt request will be generated if the SPI Interrupt Enable bit (SPIE) and the Serial Port Interrupt Enable bit (ES) are both set.
An external master drives the Slave Select input pin, SS/P1 [4], low to select the SPI module as a slave. If SS/P1 [4] has not been driven low, then the slave SPI unit is not active and the MOSI/P1 [5] port can also be used as an input port pin.
SPCR - SPI control register (address D5H) bit allocation