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11:42 AM
The AT93C46/56/66 is accessed via a simple and versatile 3-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor.
A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic “1”) followed by the appropriate Op Code and the desired memory Address location.
READ (READ): The Read (READ) instruction contains the Address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or 16-bit data output string.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the Erase/Write Enable state, programming remains enabled until an Erase/Write Disable (EWDS) instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). Logic “1” at pin DO indicates that the selected memory location has been erased, and the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle, tWP, starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). Logic “0” at DO indicates that programming is still in progress. Logic “1” indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. A READY/BUSY status cannot be obtained if the CS is brought high after the end of the self-timed programming cycle, tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLES (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the READ instruction is independent of both the EWEN and EWDS instructions and can be executed at any time.
11:41 AM
The AT93C46/56/66 provides 1024/2048/4096 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 64/128/256 words of 16 bits each, when the ORG pin is connected to VCC and 128/256/512 words of 8 bits each when it is tied to ground. The device is optimized for use in many industrial and commercial applications where low power and low voltage operations are essential. The AT93C46/56/66 is available in space-saving 8-lead PDIP and 8-lead JEDEC and EIAJ SOIC packages.
11:40 AM
• Low-voltage and Standard-voltage Operation
• User-selectable Internal Organization
• 3-wire Serial Interface
• 2 MHz Clock Rate (5V)
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade and Extended Temperature Devices Available
• 8-lead PDIP, 8-lead JEDEC and EIAJ SOIC, and 8-lead TSSOP Packages
11:40 AM
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11:40 AM
•
The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software deadlock and automatic recovery.
To protect the system against software deadlock, the user software must refresh the WDT within a user-defined time period. If the software fails to do this periodical refresh, an internal hardware reset will be initiated if enabled (WDRE = 1). The software can be designed such that the WDT times out if the program does not work properly.
• Power-on Reset
At initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algorithm has weakly pulled all pins HIGH. Powering up the device without a valid reset could cause the MCU to start executing instructions from an indeterminate location. Such undefined states may inadvertently corrupt the code in the flash.
When power is applied to the device, the RST pin must be held HIGH long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. An example of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 mF capacitor and to VSS through an 8.2 kW resistor. For a low frequency oscillator with slow start-up time the reset signal must be extended in order to account for the slow start-up time. This method maintains the necessary relationship between VDD and RST to avoid programming at an indeterminate location, which may cause corruption in the code of the flash. The power-on detection is designed to work as power-up initially, before the voltage reaches the brown-out detection level. The POF flag in the PCON register is set to indicate an initial power-up condition. The POF flag will remain active until cleared by software. Please refer to the PCON register definition for detail information. Following reset, the P89V51RD2 will either enter the Soft ICE mode (if previously enabled via ISP command) or attempt to auto baud to the ISP boot loader. If this auto baud is not successful within about 400 ms, the device will begin execution of the user code
11:38 AM
•
The software reset is executed by changing FCF [1] (SWR) from ‘0’ to ‘1’. Software reset will reset the program counter to address 0000H. All SFR registers will be set to their reset values, except FCF [1] (SWR), WDTC [2] (WDTS), and RAM data will not be altered.
• Interrupt priority and polling sequence
The device supports eight interrupt sources under a four level priority scheme. It summarizes the polling sequence of the supported interrupts. Note that the SPI serial interface and the UART share the same interrupt vector.
11:38 AM
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11:38 AM
• LSB first or MSB first data transfer
• Four programmable bit rates
• End of transmission (SPIF)
• Write collision flag protection (WCOL)
• Wake-up from idle mode (slave mode only)
SPI description
The serial peripheral interface (SPI) allows high-speed
Synchronous data transfer between the P89V51RD2 and peripheral devices or between several P89V51RD2 devices. Figure 16 shows the correspondence between master and slave SPI devices. The SCK pin is the clock output and input for the master and slave modes, respectively. The SPI clock generator will start following a write to the master devices
SPI data register. The written data is then shifted out of the MOSI pin on the master device into the MOSI pin of the slave device. Following a complete transmission of one byte of data, the SPI clock generator is stopped and the SPIF flag is set. An SPI interrupt request will be generated if the SPI Interrupt Enable bit (SPIE) and the Serial Port Interrupt Enable bit (ES) are both set.
An external master drives the Slave Select input pin, SS/P1 [4], low to select the SPI module as a slave. If SS/P1 [4] has not been driven low, then the slave SPI unit is not active and the MOSI/P1 [5] port can also be used as an input port pin.
SPCR - SPI control register (address D5H) bit allocation
11:38 AM
The UART operates in all standard modes. Enhancements over the standard 80C51 UART include Framing Error detection, and automatic address recognition.
Mode 0
Serial data enters and exits through RxD and TxD outputs the shift clock. Only 8 bits are transmitted or received, LSB first. The baud rate is fixed at 1¤6 of the CPU clock frequency. UART configured to operate in this mode outputs serial clock on TxD line no matter whether it sends or receives data on RxD line.
Mode 1
10 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0), 8 data bits (LSB first), and a stop bit (logical 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1¤2 overflow rate.
Mode 2
11 bits are transmitted (through TxD) or received (through RxD): start bit (logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or (e.g. the parity bit (P, in the PSW) could be moved into TB8). When data is received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1¤16 or 1¤32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON.
Mode 3
11 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1¤2 overflow rate.
SCON - Serial port control register (address 98H) SM0/SM1 mode definition
Framing error
Framing error (FE) is reported in the SCON.7 bit if SMOD0 (PCON.6) = 1. If SMOD0 = 0, SCON.7 is the SM0 bit for the UART, it is recommended that SM0 is set up before SMOD0 is set to ‘1’.
More about UART mode 1
Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset to align its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed.
11:04 AM
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11:03 AM
The two 16-bit Timer/Counter registers: Timer 0 and Timer 1 can be configured to operate either as timers or event counters.
In the ‘Timer’ function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of six oscillator periods, the count rate is 1¤6 of the oscillator frequency.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once every machine cycle.
When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register in the machine cycle following the one in which the transition was detected. Since it takes two machine cycles (12 oscillator periods) for 1-to-0 transition to be recognized, the maximum count rate is 1¤12 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. In addition to the ‘Timer’ or ‘Counter’ selection, Timer 0 and Timer 1 have four operating modes from which to select.
• Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a fixed divide-by-32 pre scalar. Figure shows Mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a control bit in the Special Function Register TCON (Figure 6). The GATE bit is in the TMOD register.
• Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are used.
• Mode 2
Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reloads, as shown in Figure 9. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1.
• Mode 3
When timer 1 is in Mode 3 it is stopped (holds its count). The effect is the same as setting TR1 = 0.
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for Mode 3 and Timer 0 is shown in Figure 10. TL0 uses the Timer 0 control bits: T0C/T, T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the ‘Timer 1’ interrupt.
Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, the P89V51RD2 can look like it has an additional Timer.
Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt.
• Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2 in the special function register T2CON. Timer 2 has four operating modes: Capture, Auto-reload (up or down counting), Clock-out, and Baud Rate Generator which are selected according to Table 17 using T2CON and T2MOD.
• Capture mode
In the Capture Mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 = 0 Timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which upon overflowing sets bit TF2, the Timer 2 overflow bit.
This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IEN0 register). If EXEN2 = 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively.
11:03 AM
Several In-Application Programming (IAP) calls are available for use by an application program to permit selective erasing, reading and programming of Flash sectors, pages, security bit, configuration bytes, and device id. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at 1FF0H.
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10:49 AM
Power-On reset code execution
Following reset, the P89V51RD2 will either enter the Soft ICE mode (if previously enabled via ISP command) or attempt to auto baud to the ISP boot loader. If this auto baud is not successful within about 400 ms, the device will begin execution of the user code.
Using the In-System Programming
The ISP feature allows for a wide range of baud rates to be used in your application, independent of the oscillator frequency. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the P89V51RD2 to establish the baud rate. The ISP firmware provides auto-echo of received characters. Once baud rate initialization has been performed, the ISP firmware will only accept Intel Hex-type records.
10:49 AM
The P89V51RD2 program memory consists of a 64 kB block. An In-System Programming (ISP) capability, in a second 8 kB block, is provided to allow the user code to be programmed in-circuit through the serial port. There are three methods of erasing or programming of the Flash memory that may be used. First, the Flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point (IAP). Second, the on-chip ISP boot loader may be invoked. This ISP boot loader will, in turn, call low-level routines through the same common entry point that can be used by the end-user application. Third, the Flash may be programmed or erased using the parallel method by using a commercially available EPROM programmer which supports this device.
10:47 AM
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10:40 AM
The device has separate address spaces for program and data memory.
Data RAM memory
The data RAM has 1024 bytes of internal memory. The device can also address up to 64 kB for external data memory.
Expanded data RAM addressing
The P89V51RD2 has 1 kB of RAM. See Figure 5 “Internal and external data memory structure.”
The device has four sections of internal data memory:
1. The lower 128 bytes of RAM (00H to 7FH) are directly and indirectly addressable.
2. The higher 128 bytes of RAM (80H to FFH) are indirectly addressable.
3. The special function registers (80H to FFH) are directly addressable only.
4. The expanded RAM of 768 bytes (00H to 2FFH) is indirectly addressable by the move external instruction (MOVX) and clearing the EXTRAM bit.
Since the upper 128 bytes occupy the same addresses as the SFRs, the RAM must be accessed indirectly. The RAM and SFRs space are physically separate even though they have the same addresses.
AUXR - Auxiliary register (address 8EH) bit allocation
Not bit addressable; Reset value 00H
Bit 7 6 5 4 3 2 1 0
Symbol - - - - - - EXTRAM AO
When instructions access addresses in the upper 128 bytes (above 7FH), the MCU determines whether to access the SFRs or RAM by the type of instruction given. If it is indirect, then RAM is accessed. If it is direct, then an SFR is accessed. See the examples below.
10:39 AM
There are two internal flash memory blocks in the device. Block 0 has 64 Kbytes and contains the user’s code. Block 1 contains the Philips-provided ISP/IAP routines and may be enabled such that it overlays the first 8 Kbytes of the user code memory.
The 64 kB Block 0 is organized as 512 sectors, each sector consists of 128 bytes. Access to the IAP routines may be enabled by clearing the BSEL bit in the FCF register. However, caution must be taken when dynamically changing the BSEL bit.
Since this will cause different physical memory to be mapped to the logical program address space, the user must avoid learning the BSEL bit when executing user code within the address range 0000H to 1FFFH.
10:37 AM
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10:37 AM
Special Function Registers (SFRs) accesses are restricted in the following ways:
• User must not attempt to access any SFR locations not defined.
• Accesses to any defined SFR locations must be strictly for the functions for the
• SFRs.
• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:
• ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.
– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.
– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.
10:36 AM
• 80C51 Central Processing Unit
• 5 V Operating voltage from 0 to 40 MHz
• 64 kB of on-chip Flash program memory with ISP (In-System Programming) and
• IAP (In-Application Programming)
• Supports 12-clock (default) or 6-clock mode selection via software or ISP
• SPI (Serial Peripheral Interface) and enhanced UART
• PCA (Programmable Counter Array) with PWM and Capture/Compare functions
• Four 8-bit I/O ports with three high-current Port 1 pins (16 mA each)
• Three 16-bit timers/counters
• Programmable Watchdog timer (WDT)
• Eight interrupt sources with four priority levels
• Second DPTR register
• Low EMI mode (ALE inhibit)
• TTL- and CMOS-compatible logic levels.
• Brown-out detection
• Low power modes
• Power-down mode with external interrupt wake-up
• Idle mode
• PDIP40, PLCC44 and TQFP44 packages.
10:29 AM
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10:16 AM
The Power-down mode is entered by setting the PD bit in the PCON register. In the Power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. SRAM contents are retained during Power-down; the minimum VDD level is 2.0 V.
The device exits Power-down mode through either an enabled external level sensitive interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits Power-down. Holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. Upon interrupt signal restored to logic VIH, the interrupt service routine program execution resumes beginning at the instruction immediately following the instruction which invoked Power-down mode. A hardware reset starts the device similar to power-on reset.
To exit properly out of Power-down, the reset or external interrupt should not be executed before the VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms).
10:15 AM
The device provides two power saving modes of operation for applications where power consumption is critical. The two modes are idle and Power-down.
Idle mode
Idle mode is entered setting the IDL bit in the PCON register. In idle mode, the program counter (PC) is stopped. The system clock continues to run and all interrupts and peripherals remain active. The on-chip RAM and the special function registers hold their data during this mode.
10:12 AM
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10:12 AM
The Flash program memory supports both parallel programming and in serial In-System Programming (ISP). Parallel programming mode offers gang-programming at high speed, reducing programming costs and time to market. ISP allows a device to be reprogrammed in the end product under software control. The capability to field/update the application firmware makes a wide range of applications possible. The P89V51RD2 is also In-Application Programmable (IAP), allowing the Flash program memory to be reconfigured even while the application is running.
10:11 AM
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9:09 PM
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9:03 PM
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8:26 PM
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8:07 PM
The task of identity verification is much easier than that of identity recognition: the former involving just one comparison while the latter involving multiple comparisons with fingerprints in the database. Despite these differences in the functionalities among different fingerprint identification application domains, all the underlying systems rely on the distinctive individual information in fingerprints.
8:03 PM
Fingerprint identification is based on two basic premises:
(i)persistence: the basic characteristics of fingerprints do no change with time; and (ii) individuality: the fingerprint is unique to an individual.
Since biometric identifiers cannot be easily misplaced, forged, or shared, they are considered more reliable for personal identification than traditional token or knowledge based methods. Table 1 summarizes typical applications of biometrics for positive person identification.
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7:59 PM
Behavioral biometrics is normally used for verification while physical biometrics can be used for identification and verification.
Some of physical biometrics is
Finger print - analyzing fingertip patterns.
Facial recognition – measuring facial characteristics
Hand geometry - measuring the shape of the hand
Iris recognition – analyzing features of colored ring of the eye
Vascular patterns - analyzing vein patterns
Retinal scan – analyzing blood vessels in the eye
Bertillon age – measuring body lengths (no longer used)
7:52 PM
Biometric recognition is used in identification mode. The biometric system finds a person from the enrolled population by searching a database for a match based on the biometric. For instance an entire set of data base can be searched to identify a person has not applied for entitlement benefits under two different names. This is also called one-to-many matching.
7:50 PM
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7:49 PM
Biometric devices consist of a reader or scanning device, software that converts the gathered information into digital form, and a database that stores the biometric data for comparison with previous records. When converting the biometric input, the software identifies specific points of data as match points. The match points are processed using an algorithm into a value that can be compared with biometric data in the data base.
7:46 PM
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7:40 PM
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7:39 PM
Biometrics means the statistical and mathematical strategies applied to data analysis problems in the biological sciences.
The term “biometrics” comes from the greek words bio(life) and metric (to ensure). For our use, biometrics means the technologies for measuring and analyzing a person’s physiological or behavioral characteristics, such as fingerprints, irises, voice patterns, and hand measurements, for identification and verification purposes.
7:38 PM
Biometrics is the automated identification of human identity through the measurement of repeatable physiological or behavioral characteristics”.
In simple terms identification means the search of a biometric sample against a database of other samples in order to confirm whether the donor is already present in, or new to the database.
Verification refers to the one to one comparison between a sample and another to ask the question, are you who you say you are. The majority of access control applications utilize verification techniques, rather than attempting searches of databases, which could compromise accuracy and raise costs.
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In my previous post, I have said that bdsm chat is the best way to get new good friends. Apart from getting good friends you can also have lots and lots of fun and enjoyment in the free bdsm chat. They have categorized the bdsm chat rooms, so it is very easy for the users to search the kind of people they need.
7:31 PM
Mainframe used to e defined by their size and they can still fit the room, cost millions and support thousands of users. But now a mainframe can also run on a laptop and support two users. So today’s mainframes are best supported by their operating system. UNIX and LINUX, IBMs and VSE. Reliable single thread performance, maximum I/O connectivity, maximum I?O bandwidth, reliability-Mainframe are its important features.
4:56 PM
Pushmail is the type of e-mail found on mobile phones, PDAs and other smart phones. In this type the internet connection is always on and the e-mail is immediately delivered to the device, the instant it arrives on the server. In many cases only the header may be retrieved to the handheld so that the bandwidth is not wasted. IMAP4 supports pushmail.
4:52 PM
Hi everybody. Friends are really the gift of God. No one will feel bored when they are with the friends. There are some people separated from their friends due to unavoidable conditions. Are you one among those people? Do not worry. Here comes a chance for all you people to make friends online through bdsm chat. In the bdsm chat rooms you will find lot new friends. I suggest you that free bdsm chat is the best way to get new good friends.
4:52 PM
The format of the e-mail messages is called MIME. Before MIME only plain roman text could be sent. MIME specified how other types of information to be formatted so that they can be sent along with e-mails. The mapping of MIME and other formats are automatically done by MDAs and mail servers.
4:49 PM
The globalization has its plus and minus. The Indus civilization had one of the most globalized economics of that time. Some cities specialized in the production of copper, others in beads and textiles-all meant for the export markets. Once again the period of Gupta Empire saw huge exports from India. India is known as the ‘golden bird’ though little gold is found in the country. The wealth of India in the past may be said to be substantially due to our having adopted an outward oriented trade policy.
8:39 PM
Hi everybody, a very good evening to you. In today’s world the health problems for a normal person is increasing rapidly. The main reason for this health problem is the food habit. Dental problem is one among those health problems that we cannot be able to tolerate and the dental problem occurs mainly due to the sweets and the chocolates that we eat. As we are very fond of these items we cannot avoid that. Then how to solve these problems? Here comes the solution for our dental problems and it is Dental Marketing. This is a developing website that provides the solution for our dental problems. They suggest the prevention measures that we should exercise in our daily life to avoid the dental problems. What is the solution if we are suffering from dental problems? Do not worry. They have the answer for that too. They provide you the details of the best dental doctors in the city to care of your teeth. You will find it very useful visiting this website in the future. Have a healthy life.
1:05 PM
Though we have several advantages in using the computers, there are some disadvantages too. It comes in the case of our health. There are many surveys saying that, using the computers for a long time will affect your eyes. Don’t worry there are some preventive measures are also available. It is called as 20-20 principle by the doctors. Every 20 minutes while using the computer you should see some objects at the distance of 20 meters for just 20 seconds. This will reduce the stress produced on your eyes.
1:22 AM
I still remember, it was my first day in college, our lecturer asked us a question. The question was “What would you ask if God asks you to ask him for a wish?” Many people said many answers. I told, “I will ask him to multiply the wish by 3 since I had 3 wishes”. Jokes apart, now in this very day, if some one asks me the same question, my reply would be like “I should never ever get hemorrhoids in my life. If he wishes, he can give it to my biggest enemy”. I am not joking people. This is the worst thing one can get in his health. Many people used to call hemorrhoids by the term piles. Many people would have met many people who are affected by piles complaint. I have met a piles complaint patient on a travel. I got shocked to know about piles complaint and the causes of hemorrhoids. I do not want to elaborate it and waste your valuable time. I will put it in short and simple words. If you get piles, you will not be able to sit and you will get frequent bleeding. You will not also be able to excrete properly and you have to struggle hard to excrete. And when you excrete, it will bleed again and above all you will have extreme unbearable pain all the time in you anus. The pain will get even more worse when you sit and when you excrete. On the whole, you will feel as if you live in hell. You can not be able to concentrate in your work. You will lose your temper easily and you can not sit back and relax at all. Always your mind will be in stress. Hope you remember which I have mentioned already that you will get problems in excretion. Because of this, your internal health will start getting affected. The in excretion or the improper excretion results in other illness of health. In short, if you get affected by the piles complain problem, it means that you have been cursed. Well, no illness is incurable. The piles complaint problem is no exception in this. There are lot of hemorrhoids treatments available which cures the piles complaint problem and make you get rid of the piles complaint problem completely. It is always better to go for the best treatment instead going to just another treatment. The web site which I have mentioned over here gives you the best treatment for any kind of piles complaint problems. No matter how big your problem is, they have the best solution for it. There are lots of stages in the piles complaint problem. If you are affected by the piles complaint problem, then do not worry and do not lose your confidence. You can get your problem solved in few days. Visit the site once and you can find loads of information about piles and its effects. You can get lot of guidance and support from medical expert and last but the least, you can live happily. This is the ultimate goal for any human being who lives in the world. Health is not jus wealth. It is better than wealth.
8:29 AM
Reading is one of the best habit as well as hobby that one can ever have. Doesn’t it make our mind very pleased while we are in the action? I feel it does so. Whenever I was tensed, usually my habit is going to the library and to read any short story. After then I feel relaxed.
It doesn’t stick only with this purpose as you can gain the knowledge, which is the irremovable wealth of any human being. I should thank my dad, because he is the one who made me read. Thanks dad. I hope I should carry this habit throughout my lifetime.
1:01 AM
The third test match between India and Australia begins today. After winning the toss the Indian captain Anil Kumble decided to bat. Initially the Australian bowlers trouble the Indian batsman as the first two wickets fell one after another. But then the Master batsman enters the field to rescue the team. Of course he did the rescue act perfectly. At the stumps Indians set their hands up by finishing the first day play by losing only three wickets to get the score of 296 runs.
11:49 PM
1:04 PM
This is my pen drive. I bought this pen drive one year before and used it for many purposes. It has helped me a lot during my project work for taking the back up. Sometimes my lab system won’t have the software to run my project. In such a case I will directly install the software from my pen drive and continue my presentation. As my pen drive is very small I can keep it in my purse and so that I can use it any time I want.
12:04 AM
Yes now I am going to speak about the wonderful feeling that will be experienced by every youngster in this world. If you guessed it as love then you are right. It is really a gifted opportunity to have a person who cares for us till our last minute. But in my community those who had fallen in love had to face a lot of problems. Here, to gain the love of the girl/boy you have to lose the care and affection of parents. I am fortunate that I didn’t get fall in love so that I have my parent’s love forever. I hope that you like this post.
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